MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
12-74 Freescale Semiconductor
12.6 Revision History
Table 12-25. Changes to MPC5553/5554 RM for Rev. 4.0 Release
Description of Change
• Added this sentence to the Features list, to the bullet of 32-bit address bus:
“ (necessary to configure CS[0:3] to be ADDR[8:11]to have the full 24 bits available)”
• Added this Note to section of Single Master Mode:
“On the MPC5553, the arbitration pins (BB, BR, BG) are not functional.”
• Changed pullup status of CLKOUT signal in the Signal Properties table:
from ” --”
to “Enabled”
•In Section 12.2.1.15, “Transfer Size 0–1 (TSIZ[0:1]) — MPC5554 Only, made this change to the last sentence:
From: Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1.
To: Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1 in order to run external master accesses to the
MPC5553.
• In the TSIZ section, added the sentence:
“Note that in the MPC5553, the EBI_MCR[SIZEN] bit must be set to 1.”
• In the section “Back to Back Accesses” added Figure 12-21 “Read After Write to the Same CS
Bank” and added this NOTE:
“In some cases, CS remains asserted during this dead cycle, such as the cases of back-to-back writes or read-after-write
to the same chip-select. See Figure 12-20 and Figure 12-21. “
• Added the following footnote to the Table 12-18, Transaction Sizes Supported by EBI:
“Some misaligned access cases may result in 3-byte writes. These cases are treated as power-of-2 sized requests by
the EBI, using WE
/BE[0:3] to make sure only the appropriate 3 bytes get written.”
• Added the following note to Figure 12-52 and Figure 12-55:
“On a 32-bit bus, RAM memories use all four WE/BE[0:3]. On a 16-bit bus, one RAM memory uses WE/BE[0:1] and the
other uses WE/BE[2:3].”
•In Section 12.4.2.3, “Basic Transfer Protocol, made this change:
From: “To facilitate asynchronous write support, the EBI keeps driving valid write data on the data bus until 1 clock after
the rising edge where RD_WR and WE are negated (for chip select accesses only).”
To: “To facilitate asynchronous write support, the EBI keeps driving valid write data on the data bus until 1 clock after the
rising edge where RD_WR (and WE for chip select accesses) are negated.
• Added a footnote to Table 12-5: “All I/O signals are three-stated by the EBI when not actively involved in a transfer.”
• Removed “Signal Pad Configuration by Mode” section and associated table from this version of the Reference Manual.
Table 12-26. Changes to MPC5553/5554 RM for Rev. 5.0 Release
Description of Change
• In the Data Bus Contents for Write Cycles table, blanked some of the cells in the D0:D7 and D8:D15 (32-Bit Port Size)
columns.
To Next Page
Loading...