Freescale Semiconductor MPC5553 - Modes of Operation

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 9-3
• 64-channel (MPC5554) or 32-channel (MPC5553) implementation performs complex data
transfers with minimal intervention from a host processor
— 32 bytes of data registers, used as temporary storage to support burst transfers (refer to SSIZE
bit)
— Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor (TCD) organized to support two-deep, nested transfer operations
— 32-byte TCD per channel stored in local memory
— An inner data transfer loop defined by a minor byte transfer count
— An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continual transfers
— Peripheral-paced hardware requests (one per channel)
NOTE
For all three methods, one activation per execution of the minor loop is
required
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are enabled per channel, and logically summed together to form two
optional error interrupts (MPC5554) or a single error interrupt (MPC5553).
• Support for scatter/gather DMA processing.
• Any channel can be programmed so that it can be suspended by a higher priority channel’s
activation, before completion of a minor loop.
Throughout this chapter, n is used to reference the channel number. Additionally, data sizes are defined as
byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).
9.1.4 Modes of Operation
9.1.4.1 Normal Mode
In normal mode, the eDMA is used to transfer data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
9.1.4.2 Debug Mode
If enabled by EDMA_CR[EDBG] and the CPU enters debug mode, the eDMA will not honor any service
requests when the debug input signal is asserted. If the signal is asserted during transfer of a block of data
described by a minor loop in the current active channel’s TCD, the eDMA will continue operation until
completion of the minor loop.
9.2 External Signal Description
The eDMA has no external signals.