MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
17-22 Freescale Semiconductor
17.4 Functional Description
The eMIOS provides independent channels (UC) that can be configured and accessed by the
MPC5553/MPC5554. Four time bases can be shared by the channels through four counter buses and each
unified channel can generate its own time base. Optionally, the counter A bus can be driven by an external
time base from the eTPU imported through the STAC interface.
NOTE
Counter bus A can be driven by unified channel 23 or by the STAC bus.
Counter bus B, C, and D are driven by unified channels 0, 8, and 16,
respectively. Counter bus A can be shared among all unified channels. UCs
0 to 7, 8 to 15, and 16 to 23 can share counter buses B, C, and D,
respectively.
The following four components of the MPC5553/MPC5554 eMIOS are discussed below:
• Bus interface unit
• STAC client submodule
• Global clock prescaler
• Unified channels and their modes of operation
17.4.1 Bus Interface Unit (BIU)
The bus interface unit provides the interface between the internal bus and the slave interface, allowing
communication among all submodules and the slave interface.
The BIU allows 8-, 16-, and 32-bit accesses. They are performed over a 32-bit data bus in a single cycle
clock.
17.4.1.1 Effect of Freeze on the BIU
When the FRZ bit in the EMIOS_MCR is set and the module is in debug mode, the operation of the BIU
is not affected.
17.4.2 STAC Client Submodule
The shared time and angle count (STAC) bus provides access to one external time base, imported from the
STAC bus to the eMIOS unified channels. The eTPU module's time bases and angle count can be exported
and/or imported through the STAC client submodule interface. Time bases and/or angle information of
29 UCIN Unified channel input pin. Reflects the input pin state after being filtered and synchronized.
30 UCOUT Unified channel output pin. The UCOUT bit reflects the output pin state.
31 FLAG FLAG. Set when an input capture or a match event in the comparators occurred. This bit
is cleared by writing a 1 to it.
0 FLAG cleared
1 FLAG set event has occurred
Note: When EMIOS_CCR[DMA] bit is set, the FLAG bit is cleared by the eDMA controller.
Table 17-12. EMIOS_CSRn Field Descriptions (Continued)
Bits Name Description
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