Freescale Semiconductor MPC5553 - Introduction

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 25-1
Chapter 25
Nexus Development Interface
25.1 Introduction
The MPC5553/MPC5554 microcontroller contains multiple Nexus clients that communicate over a single
IEEE-ISTO 5001™-2003 Nexus class 3 combined JTAG IEEE 1149.1/auxiliary out interface.
Combined, all of the Nexus clients are referred to as the Nexus development interface (NDI). Class 3
Nexus allows for program, data, and ownership trace of the microcontroller execution without access to
the external data and address buses.
This chapter is organized in the following manner:
• The chapter opens with sections that provide a high level view of the Nexus development interface:
Section 25.1, “Introduction” through Section 25.8, “NPC Initialization/Application Information.”
The remainder of the chapter contains sections that discuss the remaining three modules of the Nexus
development interface:
• Nexus dual-eTPU development interface (NDEDI). The MPC5554 has two eTPU engines,
whereas the MPC5553 has one eTPU engine. Refer to Section 25.9, “Nexus Dual eTPU
Development Interface (NDEDI)” and the eTPU Reference Manual for information about the
NDEDI.
• Nexus e200z6 core interface (NZ6C3). In this chapter, the NZ6C3 interface is discussed in
Section 25.10, “e200z6 Class 3 Nexus Module (NZ6C3) through Section 25.11, “NZ6C3 Memory
Map/Register Definition.”
• Nexus crossbar eDMA interface (NXDM). Refer to Section 25.12, “Nexus Crossbar eDMA
Interface (NXDM)”
Communication to the NDI is handled via the auxiliary port and the JTAG port.
• The auxiliary port is comprised of 9 or 17 output pins and 1 input pin. The output pins include 1
message clock out (MCKO) pin, 4 or 12 message data out (MDO) pins, 2 message start/end out
(MSEO) pins, 1 ready (RDY) pin, and 1 event out (EVTO) pin. Event in (EVTI) is the only input
pin for the auxiliary port.
• The JTAG port consists of four inputs and one output. These pins include JTAG compliance select
(JCOMP), test data input (TDI), test data output (TDO), test mode select (TMS), and test clock
input (TCK). TDI, TDO, TMS, and TCK are compliant with the IEEE 1149.1-2001 standard and
are shared with the NDI through the test access port (TAP) interface. JCOMP along with power-on
reset and the TAP state machine are used to control reset for the NDI module. Ownership of the
TAP is achieved by loading the appropriate enable instruction for the desired Nexus client in the
JTAG controller (JTAGC) when JCOMP is asserted. See Table 25-4 for the JTAGC opcodes to
access the different Nexus clients.