Freescale Semiconductor MPC5553 - Flash ECC Attributes Register (ECSM_FEAT); Flash ECC Master Number Register (ECSM_FEMR)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
8-8 Freescale Semiconductor
8.2.1.7 Flash ECC Master Number Register (ECSM_FEMR)
The FEMR is an 8-bit register for capturing the XBAR bus master number of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the ECSM_FEAR,
ECSM_FEMR, ECSM_FEAT and ECSM_FEDR registers, and the appropriate flag (FNCE) in the
ECSM_ESR to be asserted.
8.2.1.8 Flash ECC Attributes Register (ECSM_FEAT)
The ECSM_FEAT is an 8-bit register for capturing the XBAR bus master attributes of the last,
properly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR register, an
ECC event in the flash causes the address, attributes, and data associated with the access to be loaded into
the ECSM_FEAR, ECSM_FEMR, ECSM_FEAT, and ECSM_FEDRs, and the appropriate flag (FNCE)
in the ECSM_ESR to be asserted.
Table 8-6. ECSM_FEAR Field Descriptions
Bits Name Description
0–31 FEAR
[0:31]
Flash ECC address. Contains the faulting access address of the last, properly-enabled
flash ECC event.
01234567
R 0000 FEMR
W
Reset 0000UUUU
Reg Addr ECSM Base + 0x0056
1
“U” signifies a bit that is uninitialized. Refer to the Preface of the book.
Figure 8-5. Flash ECC Master Number Register (ECSM_FEMR)
Table 8-7. ECSM_FEMR Field Descriptions
Name
Descriptio
n
Value
0–3 — Reserved.
4–7 FEMR
[0:3]
Flash ECC master number. Contains the XBAR bus master number of the faulting access
of the last, properly-enabled flash ECC event. The reset value of this field is undefined.