MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-27
3.3.7 SPE Programming Model
Not all SPE instructions record events such as overflow, saturation, and negative/positive result. See the
description of the individual SPE instruction in the e200z6 core reference for information on which
conditions are recorded and where they are recorded. Most SPE instructions record conditions to the
SPEFSCR. Vector compare instructions store the result of the comparison into the condition register (CR).
The e200z6 core has a 64-bit architectural accumulator register that holds the results of the SPE multiply
accumulate (MAC) fixed-point instructions. The accumulator allows back-to-back execution of dependent
fixed-point MAC instructions, something that is found in the inner loops of DSP code such as filters. The
accumulator is partially visible to the programmer in that its results do not have to be explicitly read to use
them. Instead, they are always copied into a 64-bit destination GPR specified as part of the instruction. The
accumulator however, has to be explicitly cleared when starting a new MAC loop. Based upon the type of
instruction, the accumulator can hold either a single 64-bit value or a vector of two 32-bit elements.
3.4 External References
In addition to the Power Architecture instructions, the MPC5554 supports e200z6 core specific
instructions and SPE APU instructions. For further information see the following documents:
• e200z6 PowerPC
TM
Core Reference Manual
•PowerPC
TM
Microprocessor Family: The Programming Environment for 32-bit Microprocessors
• Book E: Enhanced PowerPC
TM
Architecture
• EREF: A Programmer's Reference Manual for Freescale Book E Processors
• VLEPIM: Variable Length Encoding (VLE) Extension Programming Interface Manual
• Addendum to e200z6 PowerPC
TM
Core Reference Manual: e200z6 with VLE
• Errata to e200z6 PowerPC
TM
Core Reference Manual, Rev. 0
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