Freescale Semiconductor MPC5553 - Register Descriptions

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-8 Freescale Semiconductor
9.3.1 Register Descriptions
Reading reserved bits in a register will return the value of zero. Writes to reserved bits in a register will be
ignored. Reading or writing to a reserved memory location will generate a bus error.
Many of the control registers have a bit width that matches the number of channels implemented in the
module, or 64-bits in size. These registers are implemented as two 32-bit registers, and include an “H” and
“L” suffixes, signaling the “high” and “low” portions of the control function. Note that for the MPC5553,
only the Low register is implemented for its 32 channels. High (H) registers are reserved on the MPC5553
and accessing them will generate a bus error.
Base + 0x14E0 TCD39 eDMA transfer control descriptor 39 256
Base + 0x1500 TCD43 eDMA transfer control descriptor 40 256
Base + 0x1520 TCD41 eDMA transfer control descriptor 41 256
Base + 0x1540 TCD42 eDMA transfer control descriptor 42 256
Base + 0x1560 TCD43 eDMA transfer control descriptor 43 256
Base + 0x1580 TCD44 eDMA transfer control descriptor 44 256
Base + 0x15A0 TCD45 eDMA transfer control descriptor 45 256
Base + 0x15C0 TCD46 eDMA transfer control descriptor 46 256
Base + 0x15E0 TCD47 eDMA transfer control descriptor 47 256
Base + 0x1600 TCD48 eDMA transfer control descriptor 48 256
Base + 0x1620 TCD49 eDMA transfer control descriptor 49 256
Base + 0x1640 TCD50 eDMA transfer control descriptor 50 256
Base + 0x1660 TCD51 eDMA transfer control descriptor 51 256
Base + 0x1680 TCD52 eDMA transfer control descriptor 52 256
Base + 0x16A0 TCD53 eDMA transfer control descriptor 53 256
Base + 0x16C0 TCD54 eDMA transfer control descriptor 54 256
Base + 0x16E0 TCD55 eDMA transfer control descriptor 55 256
Base + 0x1700 TCD56 eDMA transfer control descriptor 56 256
Base + 0x1720 TCD57 eDMA transfer control descriptor 57 256
Base + 0x1740 TCD58 eDMA transfer control descriptor 58 256
Base + 0x1760 TCD59 eDMA transfer control descriptor 59 256
Base + 0x1780 TCD60 eDMA transfer control descriptor 60 256
Base + 0x17A0 TCD61 eDMA transfer control descriptor 61 256
Base + 0x17C0 TCD62 eDMA transfer control descriptor 62 256
Base + 0x17E0 TCD63 eDMA transfer control descriptor 63 256
Table 9-1. eDMA 32-bit Memory Map (Sheet 5 of 5)
Address Register Name Register Description Size (bits)