Freescale Semiconductor MPC5553 - Page 328

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 9-9
9.3.1.1 eDMA Control Register (EDMA_CR)
The 32-bit EDMA_CR defines the basic operating configuration of the eDMA.
For the MPC5554 the eDMA arbitrates channel service requests in four groups (0, 1, 2, 3) of 16 channels
each; the MPC5553 arbitrates channel service requests in two groups (0, 1). For the MPC5553/MPC5554,
group 0 contains channels 0-15 and group 1 contains channels 16-31; but for the MPC5554 only, group 2
contains channels 32-47, and group 3 contains channels 48-63.
Arbitration within a group can be configured to use either a fixed priority or a round robin. In fixed
priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers (see Section 9.3.1.15). In round robin arbitration mode, the
channel priorities are ignored and the channels within each group are cycled through, from channel 15
down to channel 0, without regard to priority.
The group priorities operate in a similar fashion. In group fixed priority arbitration mode, channel service
requests in the highest priority group are executed first where priority level 3 (in the MPC5554; priority
level 1 for the MPC5553) is the highest and priority level 0 is the lowest. The group priorities are assigned
in the GRPnPRI fields of the eDMA control register (EDMA_CR). All group priorities must have unique
values prior to any channel service requests occur, otherwise a configuration error will be reported. In
group round robin mode, the group priorities are ignored and the groups are cycled through, from group 3
down to group 0, without regard to priority.
0123456789101112131415
R0000000000000 0 00
W
Reset0000000000000 0 00
Reg Addr Base + 0x0000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R GRP3PRI
1
1
This field only available in the MPC5554.
GRP2PRI
1
GRP1PRI
2
2
In the MPC5553, only bit 21 is used
GRP0PRI
3
3
In the MPC5553, only bit 23 is used
0000ERGAERCAEDBG0
W
Reset1110010000000 0 00
Reg Addr Base + 0x0000
Figure 9-2. eDMA Control Register (EDMA_CR)
Table 9-2. EDMA_CR Field Descriptions
Bits Name Description
0–15 — Reserved.
16–17 GRP3PRI Channel group 3 priority. Group 3 priority level when fixed priority group arbitration is enabled.
Note: Available only in the MPC5554
18–19 GRP2PRI Channel group 2 priority. Group 2 priority level when fixed priority group arbitration is enabled.
Note: Available only in the MPC5554