Freescale Semiconductor MPC5553 - Chapter 15; Access Timing

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 15-3
If the entire 64 data bits are written to SRAM, no read operation is performed and the ECC is calculated
across the 64-bit data bus. The 8-bit ECC is appended to the data segment and written to SRAM.
If the write operation is less than the entire 64-bit data width (1-, 2-, or 4-byte segment), the following
occurs:
1. The ECC mechanism checks the entire 64-bit data bus for errors, detecting and either correcting or
flagging errors.
2. The write data bytes (1-, 2-, or 4-byte segment) are merged with the corrected 64 bits on the data
bus.
3. The ECC is then calculated on the resulting 64 bits formed in the previous step.
4. The 8-bit ECC result is appended to the 64 bits from the data bus, and the 72-bit value is then
written to SRAM.
15.6.1 Access Timing
The system bus is a two-stage pipelined bus, which makes the timing of any access dependent on the access
during the previous clock. Table 15-2 lists the various combinations of read and write operations to SRAM
and the number of wait states used for the each operation. The table columns contain the following
information:
Current Access Lists the access operations to SRAM
Previous Access Lists the access operations that can precede the current access to SRAM
(access operation during the previous clock)
Wait States Lists the number of wait states (bus clocks) used by the access operation according
to the combination of the current and previous access operation