Freescale Semiconductor MPC5553 - Data Trace Control Register (DTC)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-40 Freescale Semiconductor
NOTE
The WT bits will only control program/data trace if the TM bits in the
development control register 1 (DC1) have not already been set to enable
program and data trace, respectively.
25.11.7 Data Trace Control Register (DTC)
The data trace control register controls whether DTM messages are restricted to reads, writes, or both for
a user programmable address range. There are two data trace channels controlled by the DTC for the
Nexus3 module. Each channel can also be programmed to trace data accesses or instruction accesses.
Table 25-31 details the data trace control register fields.
25–23 DTS
[2:0]
Data trace start control.
000 Trigger disabled
001 Use watchpoint #0 (IAC1 from Nexus1)
010 Use watchpoint #1 (IAC2 from Nexus1)
011 Use watchpoint #2 (IAC3 from Nexus1)
100 Use watchpoint #3 (IAC4 from Nexus1)
101 Use watchpoint #4 (DAC1 from Nexus1)
110 Use watchpoint #5 (DAC2 from Nexus1)
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1)
22–20 DTE
[2:0]
Data trace end control.
000 Trigger disabled
001 Use watchpoint #0 (IAC1 from Nexus1)
010 Use watchpoint #1 (IAC2 from Nexus1)
011 Use watchpoint #2 (IAC3 from Nexus1)
100 Use watchpoint #3 (IAC4 from Nexus1)
101 Use watchpoint #4 (DAC1 from Nexus1)
110 Use watchpoint #5 (DAC2 from Nexus1)
111 Use watchpoint #6 or #7 (DCNT1 or DCNT2 from Nexus1)
19–0 — Reserved.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RRWT1 RWT2 000000000000
W
Reset0000000000000000
Nexus Reg 0xD
1514131211109876543210
R 0 0 0 0 0 0 0 0 RC1 RC2 0 0 DI1 DI2 0 0
W
Reset0000000000000000
Nexus Reg 0xD
Figure 25-20. Data Trace Control Register (DTC)
Table 25-30. WT Field Descriptions (Continued)
Bits Name Description