Freescale Semiconductor MPC5553 - Reset Control

System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
6-106 Freescale Semiconductor
6.4.1.2 Pad Configuration
The pad configuration registers (SIU_PCR) in the SIU allow software control of the static electrical
characteristics of external pins. The pad configuration registers allow control over the following external
pin characteristics:
• Weak pullup/down enable/disable
• Weak pullup/down selection
• Slewrate selection for outputs
• Drive strength selection for outputs
• Input buffer enable (when direction is configured for output)
• Input hysteresis enable/disable
• Open drain/push-pull output selection
• Multiplexed function selection
• Data direction selection
The pad configuration registers are provided to allow centralized control over external pins that are shared
by more than one module. Each pad configuration register controls a single pin.
6.4.2 Reset Control
The reset controller logic is located in the SIU. Refer to the reset chapter of this manual for detail on the
reset operation.
6.4.2.1 RESET Pin Glitch Detect
The reset controller provides a glitch detect feature on the RESET pin. If the reset controller detects that
the RESET pin is asserted for more than 2 clock cycles, the event is latched. After the latch is set, if the
RESET pin is negated before 10 clock cycles elapses, the reset controller sets the RGF bit without affecting
any of the other bits in the reset status register. The RGF bit remains set until cleared by software or the
RESET pin is asserted for 10 clock cycles. The reset controller does not respond to assertions of the
RESET
pin if a reset cycle is already being processed.
6.4.3 External Interrupt
There are sixteen external interrupt inputs IRQ[0]–IRQ[15] to the SIU. The IRQ[n] inputs can be
configured for rising- or falling-edge events or both. Each IRQ[n] input has a corresponding flag bit in the
external interrupt status register (SIU_EISR). The flag bits for the IRQ
[4:15] inputs are OR’ed together to
form one interrupt request to the interrupt controller (OR function performed in the integration glue logic).
The flag bits for the IRQ
[0:3] inputs can generate either an interrupt request to the interrupt controller or
a DMA transfer request to the DMA controller. Table 6-141 shows the DMA and interrupt request
connections to the interrupt and DMA controllers.
The SIU contains an overrun request for each IRQ and one combined overrun request which is the logical
OR of the individual overrun requests. Only the combined overrun request is used in the
MPC5553/MPC5554, and the individual overrun requests are not connected.