Freescale Semiconductor MPC5553 - Address Recognition Options; Chapter 14

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 14-5
14.2.2.1 10 Mbps and 100 Mbps MII Interface
MII is the media independent interface defined by the IEEE 802.3 standard for 10/100 Mbps operation.
The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].
The speed of operation is determined by the FEC_CLK and FEC_RX_CLK signals which are driven by
the external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by
software via the serial management interface (FEC_MDC/FEC_MDIO signals) to the transceiver. Refer
to the MMFR and MSCR register descriptions as well as the section on the MII for a description of how
to read and write registers in the transceiver via this interface.
14.2.2.2 10 Mpbs 7-Wire Interface Operation
The FEC supports a 7-wire interface as used by many 10 Mbps ethernet transceivers. The
RCR[MII_MODE] bit controls this functionality. If this bit is deasserted, the MII mode is disabled and the
10 Mbps, 7-wire mode is enabled.
14.2.3 Address Recognition Options
The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),
and multicast hash match. Address recognition options are discussed in detail in Section 14.4.8, “Ethernet
Address Recognition”.
14.2.4 Internal Loopback
Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in
Section 14.4.13, “Internal and External Loopback.”
14.3 Programming Model
This section gives an overview of the registers, followed by a description of the buffers.
The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The
CSRs are used for mode control and to extract global status information. The descriptors are used to pass
data buffers and related buffer information between the hardware and software.
14.3.1 Top Level Module Memory Map
The FEC implementation requires a 1-Kbyte memory map space. This is divided into two sections of 512
bytes each. The first is used for control/status registers. The second contains event/statistic counters held
in the MIB block. Table 14-1 defines the top level memory map. All accesses to and from the FEC memory
map must be via 32-bit accesses. There is no support for accesses other than 32-bit.
Table 14-1. Module Memory Map
Address Function
FFF4_C000 (Base Address) –
FFF4_C1FF
Control/Status Registers
FFF4_C200 – FFF4_C3FF MIB Block Counters