MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-36 Freescale Semiconductor
NOTE
The EOC bits in DC1 must be programmed to trigger EVTO on watchpoint
occurrence for the EWC bits to have any effect.
25.11.2 Development Status Register (DS)
The development status register is used to report system debug status. When debug mode is entered or
exited, or an e200z6-defined low power mode is entered, a debug status message is transmitted with
DS[31:24]. The external tool can read this register at any time.
25.11.3 Read/Write Access Control/Status (RWCS)
The read write access control/status register provides control for read/write access. Read/write access
provides DMA-like access to memory-mapped resources on the system bus either while the processor is
halted, or during runtime. The RWCS register also provides read/write access status information as shown
in Table 25-29.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDBG000 LPCCHK000000000
W
Reset0000000000000000
Nexus Reg 0x4
1514131211109876543210
R0000000000000000
W
Reset0000000000000000
Nexus Reg 0x4
Figure 25-15. Development Status Register (DS)
Table 25-27. DS Field Descriptions
Bits Name Description
31–28 DBG e200z6 CPU debug mode status.
0 CPU not in debug mode
1 CPU in debug mode
27–26 LPC
[1:0]
e200z6 CPU low power mode status.
00 Normal (run) mode
01 CPU in halted state
10 CPU in stopped state
11 Reserved
25 CHK e200z6 CPU checkstop status.
0 CPU not in checkstop state
1 CPU in checkstop state
24–0 — Reserved.
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