MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 1-5
1.2 Features
This section provides a high-level description of the features found in the MPC5553 and MPC5554:
• Operating parameters
— Fully static operation, up to 132 MHz
— –40 to 150 C junction temperature
— Low power design
– Less than 1.2 Watts power dissipation
– Designed for dynamic power management of core and peripherals
– Software-controlled clock gating of peripherals
– Separate power supply for stand-by operation for portion of internal SRAM
— Fabricated in 0.13 m process
— 1.5V internal logic
— Input and output pins with 3.0V–5.5V range
– 35%/65% V
DDE
CMOS switch levels (with hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— External bus and Nexus pins support 1.62V–3.6V operation
– Selectable drive strength control
– Unused pins configurable as GPIO
— Designed with EMI reduction techniques
– Frequency modulated phase-locked loop
– On-chip bypass capacitance
– Selectable slew rate and drive strength
• High performance e200z6 core processor
— 32-bit CPU built on Power Architecture
— Thirty-two 64-bit general-purpose registers (GPRs)
— Memory management unit (MMU) with 32-entry fully-associative translation look-aside
buffer (TLB)
— Branch processing unit
— Fully pipelined load/store unit
— 32 kilobyte unified cache (in the MPC5554), 8 kilobyte unified cache (in the MPC5553) with
line locking
– 8-way set associative in the MPC5554, 2-way set associative in the MPC5553
– Two 32-bit fetches per clock
– 8-entry store buffer
– Way locking
– Supports assigning cache as instruction or data only on a per way basis
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