Freescale Semiconductor MPC5553 - Page 27

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
1-6 Freescale Semiconductor
– Supports tag and data parity
— Vectored interrupt support
— Interrupt latency < 70 ns @132MHz (measured from interrupt request to execution of first
instruction of interrupt exception handler)
— Reservation instructions for implementing read-modify-write constructs (internal SRAM and
flash)
— Signal processing engine (SPE) auxiliary processing unit (APU) operating on 64-bit GPRs
— Floating point
–IEEE 754 compatible with software wrapper
– Single precision in hardware, double precision with software library
– Conversion instructions between single precision floating point and fixed point
— Long cycle time instructions, except for guarded loads, do not increase interrupt latency in the
MPC5554/MPC5553. To reduce latency in both the MPC5553 and the MPC5554, long cycle
time instructions are aborted upon interrupt requests.
— Extensive system development support through Nexus debug module
• System bus crossbar switch (XBAR)
— 3 master ports in the MPC5554, 4 master ports in the MPC5553; 5 slave ports
— 32-bit address bus, 64-bit data bus
— Simultaneous accesses from different masters to different slaves (there is no clock penalty
when a parked master accesses a slave)
• Enhanced direct memory access (eDMA) controller
— 64 channels (MPC5554) or 32 channels (MPC5553) support independent 8-, 16-, 32-, or 64-bit
single value or block transfers.
— Supports variable sized queues and circular queues.
— Source and destination address registers are independently configured to post-increment or
remain constant.
— Each transfer is initiated by a peripheral, CPU, or eDMA channel request.
— Each eDMA channel can optionally send an interrupt request to the CPU on completion of a
single value or block transfer.
• Interrupt controller (INTC)
— 308 total interrupt vectors (MPC5554) or 212 total interrupt vectors (MPC5553)
– 278 (MPC5554) or 191 (MPC5553) peripheral interrupt requests
– plus 8 software setable sources
– plus 22 reserved interrupts in the MPC5554, 13 reserved in the MPC5553
— Unique 9-bit vector per interrupt source
— 16 priority levels with fixed hardware arbitration within priority levels for each interrupt source
— Priority elevation for shared resources
• Frequency modulated phase-locked loop (FMPLL)
— Input clock frequency from 8 MHz to 20 MHz