MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-50 Freescale Semiconductor
This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the
TCD local memory controller forces the TCD.MAJOR.E_LINK and TCD.E_SG bits to zero on any writes
to a channel’s TCD after that channel’s TCD.DONE bit is set indicating the major loop is complete.
NOTE
The user must clear the TCD.DONE bit before writing the
TCD.MAJOR.E_LINK or TCD.E_SG bits. The TCD.DONE bit is cleared
automatically by the eDMA engine after a channel begins execution.
9.6 Revision History
Table 9-25. Changes to MPC5553/5554 RM for Rev. 4.0 Release
Description of Change
• Added NOTE to these registers: SERQR, CERQR, SEEIR, CEEIR, CIRQR, CER, SSBR, CDSBR: “For the MPC5553, the
value 32-63 [bit 2 (xxxx1)] is reserved.”
• In the section on DMA Performance, made this change:
FROM: removed eDMA Peak Transfer Rate table
TO: Added an eDMA Peak Transfer Rates table (Table 9 -19 ) with revised values and with columns that show the effect
of buffering enabled and disabled.
Table 9-26. Changes to MPC5553/5554 RM for Rev. 5.0 Release
Description of Change
• In the table “DMA Request Summary for eDMA”, removed mention of Transmit Complete flag in rows for eSCIA_COMBTX
and eSCIB_COMBTX.
• In section “eDMA Microarchitecture”, in the "TCD local memory" bullet, under Memory controller section, deleted the
sentence "The hooks to a BIST controller for the local TCD memory are included in this module".
• In section “eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)”, in the second paragraph, removed the
last line "without the need to perform a read-modify-write sequence to the EDMA_IRQRH and EDMA_IRQRL".
• In the table “TCDn Field Descriptions”, BWC bit[0:1] description, added the following sentence to the BWC bit: “To minimize
start-up latency, bandwidth control stalls are suppressed for the first two system bus cycles and after the last write of each
minor loop.”
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