Freescale Semiconductor MPC5553 - Calibration Bus (MPC5553 Only)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
1-20 Freescale Semiconductor
— 10 Mbps 7-wire interface (industry standard)
• MII management interface for control and status
• Large on-chip transmit and receive FIFOs to support a variety of bus latencies
• Retransmission from the transmit FIFO after a collision
• Automatic internal flushing of the receive FIFO for runts and collisions
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
• External BD tables of user-definable size allow nearly unlimited flexibility in management of
transmit and receive buffer memory
• Ethernet channel uses DMA burst transactions to transfer data to and from external/system
memory
• Interrupts for network activity and error conditions
1.5.22 Calibration Bus (MPC5553 Only)
The calibration bus controls data transfer across the crossbar switch to/from memories or peripherals. The
bus shares the memory controller and most of the control logic with the EBI but the two buses come out
on two completely independent sets of pads. The calibration bus memory controller supports single data
rate (SDR) non-burst mode flash, SRAM, and asynchronous memories. In addition, the bus supports up to
three regions via dedicated calibration chip selects (two chip selects multiplexed with two address bits),
along with programmed region-specific attributes.
1.6 MPC5500 Family Memory Map
This section describes the MPC5500 family memory map. All addresses in the device, including those that
are reserved, are identified in the tables. The addresses represent the physical addresses assigned to each
module. Logical addresses are translated by the MMU into physical addresses.
Under software control of the MMU, the logical addresses allocated to modules may be changed on a
minimum of a 4-Kbyte boundary. Peripheral modules may be redundantly mapped. The customer must use
the MMU to prevent corruption.
Reserved register bits may be used for features in future family members. The default value of reserved
bits is zero. When writing to a register, the reserved bits default values should be written to that register.
As a general rule, when a feature is added bit field will need a non-zero value to activate it.
Reserved memory also may be used in future family members. These areas should not be used if reserved.
Table 1-2 shows a detailed memory map.