MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 18-1
Chapter 18
Enhanced Time Processing Unit (eTPU)
18.1 Introduction
The enhanced time processing unit (eTPU) is a new timing unit featured on the MPC5553/MPC5554
microcontroller that operates in parallel with the MPC5553/MPC5554 core (CPU). The eTPU does the
following:
• Executes programs independently from the host core
• Detects and precisely records timing of input events
• Generates complex output waveforms
• Is controlled by the core without a requirement for real-time host processing
The host core setup and service times for each input and output event are greatly minimized. The
MPC5554 contains two eTPUs, and the MPC5553 contains one.
The eTPU improves the performance of the MPC5553/MPC5554 by providing high resolution timing:
• eTPU dedicated channels that include two match and two capture registers, as opposed to the
previous generation TPUs which only had one of each register
• eTPU engines that are optimized with specific instructions to service channel hardware
• The fast instruction execution rate of the eTPU engine that reduces service time
Because responding to hardware service requests is primarily done by the eTPU engine, the host is free to
handle higher level operations.
18.1.1 The MPC5553/MPC5554 eTPU Implementation
For more detailed information regarding the eTPU module and compiler, refer to the Enhanced Time
Processing (eTPU) Reference Manual. The MPC5553/MPC5554 devices contain a specific
implementation of the eTPU’s full functionality. This chapter will focus only on an eTPU overview and
those details that are different than the full instantiation of the module. These differences include the
following:
• 3 (MPC5554) or 2.5 (MPC5553) Kbytes of shared data memory (SDM). This memory is
alternately referred to as eTPU shared parameter (data) RAM (SPRAM).
• 16 Kbytes (MPC5554) or 12 Kbytes (MPC5553) of shared code memory (SCM).
• For the MPC5553, only one eTPU engine: eTPU A in the eTPU reference manual. Ignore any
references to eTPU B.
• The eTPU debug interface is built into the MPC5553/MPC5554’s debug module. Refer to Section
10.2.1 of the eTPU reference manual for details on eTPU debug.
• Data transfer requests are implemented as a single DMA request to the MPC5553/MPC5554’s
DMA controller. All 32 channels’ data transfer request signals are logically ORed to produce the
single DMA request.
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