MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 17-3
17.1.2 Overview
The eMIOS builds on the MIOS concept by using a unified channel module that provides a superset of the
functionality of all the individual MIOS channels, while providing a consistent user interface. This allows
more flexibility as each unified channel can be programmed for different functions.
17.1.3 Features
• 24 unified channels
• Unified channels features
— 24-bit registers for captured/match values
— 24-bit internal counter
— Internal prescaler
— Dedicated output pin for buffer direction control
— Selectable time base
— Can generate its own time base
• Four 24-bit wide counter buses
— Counter bus A can be driven by unified channel 23 or by the STAC bus.
— Counter bus B, C, and D are driven by unified channels 0, 8, and 16, respectively.
— Counter bus A can be shared among all unified channels. UCs 0 to 7, 8 to 15, and 16 to 23 can
share counter buses B, C, and D, respectively.
• One global prescaler
• Shared time bases through the counter buses
• Synchronization among internal and external time bases
• Shadow FLAG register
• State of module can be frozen for debug purposes
• DMA request capability for some channels
• Motor control capability
17.1.4 Modes of Operation
17.1.4.1 eMIOS Modes
The eMIOS operates in one of the modes described below:
• User mode
This is the normal operating mode. When EMIOS_MCR[FRZ] = 0, and EMIOS_CCR[FREN] =
0, the eMIOS is in user mode.
• Debug mode
Debug mode is individually programmed for each channel. When entering this mode, the UC
registers’ contents are frozen, but remain available for read and write access through the slave
interface. After leaving debug mode, all counters that were frozen upon debug mode entry will
resume at the point where they were frozen.
In debug mode, all clocks are running and all registers are accessible; thus, this mode is not
intended for power saving, but for use during software debugging.
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