MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
10-10 Freescale Semiconductor
10.3.1 Register Descriptions
With the exception of the INTC_SSCIn and INTC_PSRn registers, all of the registers are 32 bits in width.
Any combination of accessing the 4 bytes of a register with a single access is supported, provided that the
access does not cross a register boundary. These supported accesses include types and sizes of 8 bits,
aligned 16 bits, and aligned 32 bits.
Although INTC_SSCIn and INTC_PSRn are 8 bits wide, they can be accessed with a single 16-bit or
32-bit access, provided that the access does not cross a 32-bit boundary.
In software vector mode, the effects of a read of the INTC interrupt acknowledge register (INTC_IACKR)
are the same regardless of the size of the read. In either software or hardware vector mode, the size of a
write to the INTC end-of-interrupt register (INTC_EOIR) does not affect the operation of the write.
10.3.1.1 INTC Module Configuration Register (INTC_MCR)
The INTC_MCR is used to configure options of the INTC.
0123456789101112131415
R0000000000 0 0000 0
W
Reset0000000000 0 0000 0
Reg Addr Base (0xFFF4_8000)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000000VTES0000HVEN
W
Reset0000000000 0 0000 0
Reg Addr Base (0xFFF4_8000)
Figure 10-8. INTC Module Configuration Register (INTC_MCR)
Table 10-3. INTC_MCR Field Descriptions
Bits Name Description
0–25 — Reserved.
26 VTES Vector table entry size. Controls the number of ‘0’s to the right of INTVEC in
Section 10.3.1.3, “INTC Interrupt Acknowledge Register (INTC_IACKR). If the contents of
INTC_IACKR are used as an entry address to a vector table as in software vector mode,
then the number of rightmost ‘0’s determines the size of each vector table entry.
VTES impacts software vector mode operation but also affects INTC_IACKR[INTVEC]
position in both hardware vector mode and software vector mode.
0 4 bytes (Normal expected use)
1 8 bytes
To Next Page
Loading...