MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 10-11
10.3.1.2 INTC Current Priority Register (INTC_CPR)
The INTC_CPR masks any peripheral or software settable interrupt request set at the same or lower
priority as the current value of the INTC_CPR[PRI] field from generating an interrupt request to the
processor. When the INTC interrupt acknowledge register (INTC_IACKR) is read in software vector
mode or the interrupt acknowledge signal from the processor is asserted in hardware vector mode, the
value of PRI is pushed onto the LIFO, and PRI is updated with the priority of the preempting interrupt
request. When the INTC end-of-interrupt register (INTC_EOIR) is written, the LIFO is popped into the
INTC_CPR’s PRI field.
The masking priority can be raised or lowered by writing to the PRI field, supporting the PCP. Refer to
Section 10.5.5, “Priority Ceiling Protocol.”
NOTE
On some MPC55xx MCUs, a store to raise the PRI field which closely
precedes an access to a shared resource can result in a non-coherent access
to that resource unless an mbar or msync followed by an isync sequence of
instructions is executed between the accesses. An mbar or msync
instruction is also necessary after accessing the resource but before lowering
the PRI field. Refer to Section 10.5.5.2, “Ensuring Coherency.”
27–30 — Reserved.
31 HVEN Hardware vector enable. Controls whether the INTC is in hardware vector mode or
software vector mode. Refer to Section 10.1.4, “Modes of Operation”, for the details of the
handshaking with the processor in each mode.
0 Software vector mode
1 Hardware vector mode
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
Reg Addr Base + 0x0008
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R000000000000 PRI
W
Reset0000000000001111
Reg Addr Base + 0x0008
Figure 10-9. INTC Current Priority Register (INTC_CPR)
Table 10-3. INTC_MCR Field Descriptions
Bits Name Description
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