MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor B-5
B.3.1 MPC5554 Calibration Bus Implementation
On the MPC5554 device there are no signals dedicated for calibration usage, and instead signals that are
available for normal application usage must be shared for calibration. The calibration bus signals on the
VertiCal connector (CAL_DATA, CAL_ADDR, CAL_CS etc.) are connected to the equivalent signals on
the standard MPC5554 EBI. To allow calibration, all of the MPC5554 EBI signals included in the VertiCal
connector and used by attached VertiCal top board must be available and configured for their primary EBI
mode of operation. This requirement prohibits the use of required EBI signals as general purpose IO
(GPIO) by the application. If the application itself uses the EBI to access external memory mapped
devices, the application design must ensure that sufficient resources such as chip selects and addressing
range are left available for calibration use. Because the calibration bus is shared with the standard device
system bus, the bus loading of the pins may need to be adjusted for pins that are connected to both the
standard bus and the calibration bus. The bus load for each signal is adjustable in the Pad Configuration
Register for that pin.
B.3.2 MPC5553 Calibration Bus Implementation
The MPC5553 device is similar to the MPC5554 in that no signals are dedicated for calibration usage.
Instead, signals that are available for normal application usage must be shared for calibration. The
MPC5553 differs from the MPC5554 in that the calibration bus signals on the VertiCal connector are not
all directly connected to the equivalent signals on the standard EBI. Instead some calibration pins are
implemented as secondary functions on pins that are not normally needed. The purpose of this is to
minimize the number of signals that must be reserved for calibration on applications that use the 324 BGA
packaged device.
B.4 Signals and Pads
The following sections detail the signal descriptions for the calibration bus.
B.4.1 CAL_CS[0,2:3] — Calibration Chip Selects 0, 2-3 — MPC5553
Only
CAL_CS[n] is asserted by the master to indicate that this transaction is targeted for a particular calibration
memory bank.
The calibration chip selects are driven by the EBI. CAL_CS[n] is driven in the same clock as the assertion
of TS and valid address, and is kept valid until the cycle is terminated. Bus timing is identical to standard
EBI timing.
B.4.1.1 Number of Chip Selects and Maximum Memory Size — MPC5553
The trade-off between calibration chip selects and address lines is the same as the trade-off between
non-calibration chip selects and address lines for the 324 pin package.
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