MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
5-10 Freescale Semiconductor
Presence or absence of a module’s 4-bit access field in either a PBRIDGE_x_PACR or
PBRIDGE_x_OPACR is based on whether the associated peripheral is present on the device. When
absent, the corresponding field is not implemented and will read as 0’s. Writes will be ignored.
NOTE
Table 5-6 lists all of the access fields in the PACRs and OPACRs in both
PBRIDGE_A and PBRIDGE_B, and each of the associated peripherals
present on the MPC5553/MPC5554.
2, 6, 10, 14, 18,
22, 26, 30
WPn Write protect. Determines whether the peripheral allows write accesses. Write
accesses allowed by default.
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is
terminated with an error response and no peripheral access is initiated on the
slave bus.
3, 7, 11, 15, 19,
23, 27, 31
TPn Trusted protect. Determines whether the peripheral allows accesses from an
untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted
by an untrusted master, the access is terminated with an error response and no
peripheral access is initiated on the slave bus.
1
In PBRIDGE_A_PACR0 and PBRIDGE_B_PACR0, the BW0 bit is not writable.
Table 5-6. PACR/OPACR Access Control Registers and Peripheral Mapping
Register Register Address
Peripheral
Access Field #
Peripheral
Type
Access Field
Default Value
PBRIDGE_A
PBRIDGE_A_PACR0 PBRIDGE_A_Base + 0x020 0 PBRIDGE_A 0b0101
1-7 — 0b0000
PBRIDGE_A_OPACR0 PBRIDGE_A_Base + 0x040 0 FMPLL 0b0100
1 EBI Control 0b0100
2 Flash Control 0b0100
3 — 0b0100
4 SIU 0b0100
5-7 — 0b0100
PBRIDGE_A_OPACR1 PBRIDGE_A_Base + 0x044 0 eMIOS 0b0100
1-7 — 0b0100
Table 5-5. PBRIDGE_x_PACRn and PBRIDGE_x_OPACRn
Field Descriptions (Continued)
Bits Name Description
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