MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-20 Freescale Semiconductor
11.4 Functional Description
This section explains clock architecture, clock operation, and clock configuration.
11.4.1 Clock Architecture
This section describes the clocks and clock architecture in the MPC5553/MPC5554 MCU.
11.4.1.1 Overview
The MPC5553/MPC5554 system clocks are generated from one of four FMPLL modes: crystal reference
mode, external reference mode, dual-controller (1:1) mode, and bypass mode. See Section 11.1,
“Introduction” for information on the different clocking modes available in the MPC5553/MPC5554
FMPLL.
The MPC5553/MPC5554 peripheral IP modules have been designed to allow software to gate the clocks
to the non-memory-mapped logic of the modules.
The MPC5553/MPC5554 MCU has three clock output pins that are driven by programmable clock
dividers. The clock dividers divide the system clock down by even integer values. The three clock output
pins are the following:
• CLKOUT – External address/data bus clock
• MCKO – Nexus auxiliary port clock
• ENGCLK – Engineering clock
The MPC5553/MPC5554 MCU has been designed so that the oscillator clock can be selected as the clock
source for the CAN interface in the FlexCAN blocks resulting in very low jitter performance.
Figure 11-1 shows a block diagram of the FMPLL and the system clock architecture.
11.4.1.2 Software Controlled Power Management/Clock Gating
Some of the IP modules on MPC5553/MPC5554 support software controlled power management/clock
gating whereby the application software can disable the non-memory-mapped portions of the modules by
writing to module disable (MDIS) bits in registers within the modules. The memory-mapped portions of
the modules are clocked by the system clock when they are being accessed. The NPC can be configured
to disable the MCKO signal when there are no Nexus messages pending. The H7FA flash array can be
disabled by writing to a bit in the flash register map.
The modules that implemented software controlled power management/clock gating are listed in
Table 11-7 along with the registers and bits that disable each module. The software controlled clocks are
enabled when the MPC5553/MPC5554 MCU comes out of reset.
Table 11-7. Software Controlled Power Management/Clock Gating Support
Module Name Register Name Bit Names
DSPI A
1
DSPI_A_MCR MDIS
DSPI B DSPI_B_MCR MDIS
DSPI C DSPI_C_MCR MDIS
DSPI D DSPI_D_MCR MDIS
EBI EBI_MCR MDIS
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