MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
11-2 Freescale Semiconductor
11.1.1.1 FMPLL and Clock Architecture
Figure 11-1. FMPLL Block and Clock Architecture
OSC
EXTAL_EXTCLK
PFD/
Charge
Filter RFD
Bus Interface
Control/Status
Registers
Successive
Approximation
Frequency
FM
Control
1
0
Pumps
Current
Controlled
Oscillator
(ICO)
XTAL
PREDIV
0
1
MFD
PLLCFG[0:1]
MDIS
DSPI x 4
MCKO_EN
MCKO_GT
MCKO
Divider
MCKO
MDIS
EBI
MDIS
eMIOS
MDIS
eTPU Engines
MDIS
eSCI x 2
MDIS
CAN Interface CLK
FlexCAN x 3
CLK_SRC
Message Buffer CLK
ENGCLK
Divider
CLKOUT
Divider
ENGCLK
CLKOUT
NPC
PLLREF
PLLSEL
MODE
Core, INTC, eDMA, SIU, BAM,
RAMs, eQADC, Flash, XBAR,
PBRIDGE_A, PBRIDGE_B
Oscillator Clock
SIU
System
Clock
RSTCFG
PLLCFG
[0]
PLLCFG
[1]
Clock
Mode
MODE PLLSEL PLLREF
1
PLLCFG Pins
Ignored
Crystal
Ref
(Default)
11 1
000
Bypass
Mode
00 0
001
External
Ref
11 0
010
Crystal
Ref
11 1
011
1:1
Mode
10 0
1
0
PLL
(3 in MPC5553)
(2 in MPC5553)
F
prediv
F
ref_crystal
F
ref_ext
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