Freescale Semiconductor MPC5553 - Chapter 17; Bus Interface Unit (BIU)

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-25
3.3.4 Bus Interface Unit (BIU)
The BIU encompasses control and data signals supporting instruction and data transfers. A data bus width
of 64-bits is implemented. The memory interface supports read and write transfers of 8, 16, 24, 32, and 64
bits, supports burst transfers of four doublewords, and operates in a pipelined fashion.
Decrementer IVOR 10 EE, DIE SRR[0:1] Decrementer timeout, and as specified in Book E:
Enhanced PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg.
194-195 and in the e200Z6 PowerPC
tm
Core Reference
Manual, Rev 0.
Fixed Interval
Timer
IVOR 11 EE, FIE SRR[0:1] Fixed-interval timer timeout and as specified in Book E:
Enhanced PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg.
195-196 and in the e200Z6 PowerPC
tm
Core Reference
Manual, Rev 0.
Watchdog
Timer
IVOR 12 CE, WIE CSRR[0:1] Watchdog timeout: as specified in Book E: Enhanced
PowerPC
TM
Architecture, Rev 1.0, Ch. 8, pg. 196-197 and in
the e200Z6 PowerPC
TM
Core Reference Manual, Rev 0.
Data TLB Error IVOR 13 — SRR[0:1] Data translation lookup did not match a valid entry in the
TLB
Instruction TLB
Error
IVOR 14 — SRR[0:1] Instruction translation lookup did not match a valid entry in
the TLB
Debug IVOR 15 DE, IDM CSSR[O:1] Debugger when HIDO[DAPUEN] = 0. Caused by Trap,
Instruction Address Compare, Data Address Compare,
Instruction Complete, Branch Taken, Return from Interrupt,
Interrupt Taken, Debug Counter, External Debug Event,
Unconditional Debug Event
DE, IDM DSRR[0:1] Debugger when HIDO[DAPUEN] = 1, and caused by same
conditions as above.
Reserved IVOR 16-31
SPE
Unavailable
Exception
IVOR 32 — SRR[0:1] SPE APU instruction when MSR[SPE] = 0, and see Section
5.6.18 “SPE APU Unavailable Interrupt” in the e200Z6
PowerPC
TM
Core Reference Manual, Rev 0.
SPE Data
Exception
IVOR 33 — SRR[0:1] SPE FP data exception and see Section 5.6.19 “SPE
Floating-Point Data Interrupt” in the e200Z6 PowerPC
TM
Core Reference Manual, Rev 0.
SPE Round
Exception
IVOR 34 — SRR[0:1] Inexact result from floating-point instruction. See Section
5.6.20 “SPE Floating-Point Round Interrupt” in the e200Z6
PowerPC
TM
Core Reference Manual, Rev 0.
1
CE, ME, EE, DE are in the MSR. DIE, FIE, and WIE are in the TCR. “src” signifies the individual enable for each INTC source.
The debug interrupt, IVOR 15, also requires EDM = 0 (EDM and IDM are in the DBCR0 register).
Table 3-9. Interrupts and Conditions (Continued)
Interrupt Type
Interrupt
Vector Offset
Register
Enables
1
Core Register
in Which
State
Information is
Saved
Causing Conditions