MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
25-6 Freescale Semiconductor
25.2.1.3 Message Data Out (MDO[3:0/11:0])
Message data out (MDO) are output pins used for uploading OTM, BTM, DTM, and other messages to
the development tool. The development tool should sample MDO on the rising edge of MCKO. The width
of the MDO bus used is determined by the Nexus PCR[FPM] configuration.
Following a power-on reset, MDO0 remains asserted until power-on reset is exited and the system clock
achieves lock.
25.2.1.4 Message Start/End Out (MSEO[1:0])
MSEO[1:0] are output pins that indicates when a message on the MDO pins has started, when a variable
length packet has ended, or when the message has ended. The development tool should sample the MSEO
pins on the rising edge of MCKO.
25.2.1.5 Ready (RDY)
RDY is an output pin that indicates when a device is ready for the next access.
25.2.1.6 JTAG Compliancy (JCOMP)
The JCOMP signal enables or disables the TAP controller. The TAP controller is enabled when JCOMP
asserted, otherwise the TAP controller remains in reset.
25.2.1.7 Test Data Output (TDO)
The TDO pin transmits serial output for instructions and data. TDO is tri-stateable and is actively driven
in the SHIFT-IR and SHIFT-DR controller states. TDO is updated on the falling edge of TCK and sampled
by the development tool on the rising edge of TCK.
25.2.1.8 Test Clock Input (TCK)
The TCK pin is used to synchronize the test logic and control register access through the JTAG port.
25.2.1.9 Test Data Input (TDI)
The TDI pin receives serial test instruction and data. TDI is sampled on the rising edge of TCK.
25.2.1.10 Test Mode Select (TMS)
The TMS pin is used to sequence the IEEE 1149.1-2001 TAP controller state machine. TMS is sampled
on the rising edge of TCK.
25.3 Memory Map
The NDI block contains no memory mapped registers. Nexus registers are accessed by the development
tool via the JTAG port using a register index and a client select value. The client select is controlled by
loading the correct access instruction into the JTAG controller; refer to Section 25.4.1. OnCE registers are
accessed by loading the appropriate value in the RS[0:6] field of the OnCE command register (OCMD)
via the JTAG port.
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