Freescale Semiconductor MPC5553 - On-Chip ADC Registers

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
19-36 Freescale Semiconductor
19.3.3 On-Chip ADC Registers
This section describes a list of registers that control on-chip ADC operation. The ADC registers are not
part of the CPU accessible memory map. These registers can only be accessed indirectly through
configuration commands. There are five non memory mapped registers per ADC, five for ADC0 and five
for ADC1. The address, usage, and access privilege of each register is shown in Table 19-25 and
Table 19-26. Data written to or read from reserved areas of the memory map is undefined.
Their assigned addresses are the values used to set the ADC_REG_ADDRESS field of the read/write
configuration commands bound for the on-chip ADCs. These are halfword addresses. Further, the
following restrictions apply when accessing these registers:
• Registers ADC0_CR, ADC0_GCCR, and ADC0_OCCR can only be accessed by configuration
commands sent to the ADC0 command buffer.
• Registers ADC1_CR, ADC1_GCCR, and ADC1_OCCR can only be accessed by configuration
commands sent to the ADC1 command buffer.
• Registers ADC_TSCR and ADC_TBCR can be accessed by configuration commands sent to the
ADC0 command buffer or to the ADC1 command buffer. A data write to ADC_TSCR through a
configuration command sent to the ADC0 command buffer will write the same memory location
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
Reg Addr RFIFO0: Base + 0x0300 (RF0R0); Base + 0x0304 (RF0R1); Base + 0x0308 (RF0R2); Base+0x030C (RF0R3)
RFIFO1: Base + 0x0340 (RF1R0); Base + 0x0344 (RF1R1); Base + 0x0348 (RF1R2); Base + 0x034C (RF1R3)
RFIFO2: Base + 0x0380 (RF2R0); Base + 0x0384 (RF2R1); Base + 0x0388 (RF2R2); Base + 0x038C (RF2R3)
RFIFO3: Base + 0x03C0 (RF3R0); Base + 0x03C4 (RF3R1); Base + 0x03C8 (RF3R2); Base + 0x03CC (RF3R3)
RFIFO4: Base + 0x0400 (RF4R0); Base + 0x0404 (RF4R1); Base + 0x0408 (RF4R2); Base + 0x040C (RF4R3)
RFIFO5: Base + 0x0440 (RF5R0); Base + 0x0444 (RF5R1); Base + 0x0448 (RF5R2); Base + 0x044C (RF5R3)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R RFIFO[0–5]_DATAn
W
Reset0000000000000000
Reg Addr RFIFO0: Base + 0x0300 (RF0R0); Base + 0x0304 (RF0R1); Base + 0x0308 (RF0R2); Base+0x030C (RF0R3)
RFIFO1: Base + 0x0340 (RF1R0); Base + 0x0344 (RF1R1); Base + 0x0348 (RF1R2); Base + 0x034C (RF1R3)
RFIFO2: Base + 0x0380 (RF2R0); Base + 0x0384 (RF2R1); Base + 0x0388 (RF2R2); Base + 0x038C (RF2R3)
RFIFO3: Base + 0x03C0 (RF3R0); Base + 0x03C4 (RF3R1); Base + 0x03C8 (RF3R2); Base + 0x03CC (RF3R3)
RFIFO4: Base + 0x0400 (RF4R0); Base + 0x0404 (RF4R1); Base + 0x0408 (RF4R2); Base + 0x040C (RF4R3)
RFIFO5: Base + 0x0440 (RF5R0); Base + 0x0444 (RF5R1); Base + 0x0448 (RF5R2); Base + 0x044C (RF5R3)
Figure 19-18. eQADC RFIFOn Registers (EQADC_RF[0–5]Rn)
Table 19-24. EQADC_RF[0–5]Rn Field Descriptions
Bits Name Description
0–31 RFIFO[0–5]_DATAn
[0:15]
RFIFO[0–5] data n. Returns the value stored within the entry of RFIFO[0–5]. Each
RFIFO is composed of four 16-bit entries, with register 0 being mapped to the entry
with the smallest memory mapped address.