Freescale Semiconductor MPC5553 - Initialization;Application Information

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 10-33
Figure 10-15. Hardware Vector Mode Handshaking Timing Diagram
10.5 Initialization/Application Information
10.5.1 Initialization Flow
After exiting reset, all of the PRIn fields in INTC priority select registers (INTC_PSR0–INTC_PSR307)
will be zero, and PRI in INTC current priority register (INTC_CPR) will be 15. These reset values will
prevent the INTC from asserting the interrupt request to the processor. The enable or mask bits in the
peripherals are reset such that the peripheral interrupt requests are negated. An initialization sequence for
allowing the peripheral and software settable interrupt requests to cause an interrupt request to the
processor is:
interrupt_request_initialization:
configure VTES and HVEN in INTC_MCR
configure VTBA in INTC_IACKR
raise the PRIn fields in INTC_PSRn
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR to zero
enable processor recognition of interrupts
10.5.2 Interrupt Exception Handler
These example interrupt exception handlers use Power Architecture embedded category assembly code.
10.5.2.1 Software Vector Mode
interrupt_exception_handler:
code to create stack frame, save working register, and save SRR0 and SRR1
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
0 108
0
108
01