MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor B-7
B.4.3 CLKOUT
CLKOUT is supplied by the clock control block, not the EBI. Nevertheless, the same CLKOUT is used
for both the non-calibration and calibration bus.
A drawback of having just one CLKOUT is that while the difference in board timing can be compensated
by the adjustment in the drive strength, the CLKOUT timing, and hence the timing of the non-calibration
bus, can have minor differences with a calibration tool from the production package.
B.5 Packaging
The addition of the calibration bus means that the device has more pads than can be connected to the balls
on a 416 pin package. Therefore, the die is assembled in a 496 pin chip scale package (CSP) and this
package is used in the VertiCal base assembly.
B.6 Application Information
B.6.1 Communication With Development Tool Using I/O
The development tool can require some I/Os for communication between the MCU and the development
tool on the VertiCal connector. ETRIG[0:1] and GPIO[205] are available only in the 416 pin package.
Because the application can not use these pins in the 208 and 324 pin packages, they are candidates for
development tool use in a VertiCal connector. Using ETRIG[1] and GPIO[205] still leaves ETRIG[0] for
the application in the 416 package.
B.6.2 Matching Access Delay to Internal Flash With Calibration
Memory
One use of VertiCal in the automotive environment is engine calibration. For this application, an SRAM
top board is added onto the VertiCal connector. This allows the engine calibrator to modify settings in
SRAM, possibly using the Nexus interface or even by using the eSCI port or a FlexCAN interface.
See Table 13-2 “Internal Flash External Emulation Mode.”
After the data is calibrated, it can be copied into the internal flash. The internal flash can be accessed faster
than the calibration memory and this change in calibration data access time could change the overall
system performance. To mitigate this change in system performance, the internal flash memory includes a
feature that allows accesses to portions of the flash to be slowed down by adding extra wait states. This is
done by multiply mapping the internal flash at different locations with different numbers of wait states.
For example, the physical address of the flash array is 0x0000_0000 to 0x00FF_FFFF (depending on array
size). That same flash data can be accessed at address 0x0100_0000 to 0x01FF_FFFF but accesses will be
1 clock cycle slower. That same flash data can be accessed at addresses 0x0200_0000 to 0x02FF_FFFF
but accesses will be 2 clock cycles slower. This pattern is repeated through the memory map to addresses
0x1F00_0000 to 0x1FFF_FFFF where accesses will be 31 clock cycles slower.
The application would use this feature by mapping the calibration data to a region of the flash memory that
has access timing to match the timing of the calibration RAM used when calibrating the data. This
remapping of calibration data can be achieved by either using the translation feature of the MMU or
rebuilding the code with a modified link file.
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