Freescale Semiconductor MPC5553 - Core-Specific Registers

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
3-10 Freescale Semiconductor
• Debug facility registers
— Debug control registers (DBCR0–DBCR2). These registers provide control for enabling and
configuring debug events.
— Debug status register (DBSR). This register contains debug event status.
— Instruction address compare registers (IAC1–IAC4). These registers contain addresses and/or
masks which are used to specify instruction address compare debug events.
— Data address compare registers (DAC1, DAC2). These registers contain addresses and/or
masks which are used to specify data address compare debug events.
— e200z6 does not implement the data value compare registers (DVC1, DVC2).
• Timer registers
— The clock inputs for the timers are connected to the internal system clock.
— Time base (TB). The TB is a 64-bit structure provided for maintaining the time of day and
operating interval timers. The TB consists of two 32-bit registers, time base upper (TBU) and
time base lower (TBL). The time base registers can be written to only by supervisor-level
software, but can be read by both user and supervisor-level software.
— Decrementer register (DEC). This register is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay.
— Decrementer auto-reload (DECAR). This register is provided to support the auto-reload feature
of the Decrementer.
— Timer control register (TCR). This register controls decrementer, fixed-interval timer, and
watchdog timer options.
— Timer status register (TSR). This register contains status on timer events and the most recent
watchdog timer-initiated processor reset.
More details about these registers can be found in the Power Architecture embedded category
specifications.
3.2.2 Core-Specific Registers
The Power Architecture embedded category allows implementation-specific registers. Those incorporated
in the e200z6 core are as follows:
3.2.2.1 User-Level Registers
The user-level registers can be accessed by all software with either user or supervisor privileges. They
include the following:
• Signal processing extension APU status and control register (SPEFSCR). The SPEFSCR contains
all fixed-point and floating-point exception signal bits, exception summary bits, exception enable
bits, and rounding control bits needed for compliance with the IEEE 754 standard.
• The L1 cache configuration register (L1CFG0). This read-only register allows software to query
the configuration of the L1 Unified cache.
3.2.2.2 Supervisor-Level Registers
The following supervisor-level registers are defined in e200z6 core in addition to the Power Architecture
embedded category registers described above:
• Configuration registers