MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 4-3
4.2.5 Boot Configuration (BOOTCFG[0:1])
In the MPC5554, BOOTCFG determines the function and state of the following pins after execution of the
BAM reset: CS[0:3], ADDR[12:31], DATA[0:31], TSIZ[0:1], RD_WR, BDIP, WE[0:3], OE, TS, TA,
TEA, BR, BG, BB.
In the MPC5553, BOOTCFG determines the function and state of the following pins after a BAM reset:
CS[0:3], ADDR[8:31], DATA[0:31], RD_WR, BDIP, WE[0:3], OE, TS, TA, TEA. Refer to Table 4-11.
Note that BOOTCFG0 does not function in the 208 pin package of the MPC5553.
4.3 Memory Map/Register Definition
Table 4-1 summarizes the reset controller registers. The base address of the system integration unit is
0xC3F9_0000.
4.3.1 Register Descriptions
This section describes all the reset controller registers. It includes details about the fields in each register,
the number of bits per field, the reset value of the register, and the function of the register.
4.3.1.1 Reset Status Register (SIU_RSR)
The reset status register (SIU_RSR) reflects the most recent source, or sources, of reset. This register
contains one bit for each reset source. A bit set to logic 1 indicates the type of reset that occurred.
Simultaneous reset requests cause more than one bit to be set at the same time. After it is set, the reset
source bits in the SIU_RSR remain set until another reset occurs. A software external reset causes the
SERF bit to be set, but no previously set bits in the SIU_RSR will be cleared. Additional information about
the SIU_RSR may be found in Section 6.3.1.2, “Reset Status Register (SIU_RSR).”
The SIU_RSR also contains the values latched at the last reset on the WKPCFG and BOOTCFG[0:1] pins
and a RESET
input pin glitch flag. The reset glitch flag bit (RGF) is cleared by writing a 1 to the bit. A
write of 0 has no effect on the bit state. The SIU_RSR can be read at all times.
Table 4-1. Reset Controller Memory Map
Address Register Name Register Description Size (bits)
Base (0xC3F9_000C) + 0x000C SIU_RSR Reset status register 32
Base (0xC3F9_000C) + 0x0010 SIU_SRCR System reset control register 32
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