MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-3
The e200z6 core complex is built on a single-issue, 32-bit Power Architecture design with 64-bit
general-purpose registers (GPRs). Power architecture floating-point instructions are not supported in
hardware, but are trapped and may be emulated by software. A signal processing extension (SPE) auxiliary
processing unit (APU) is provided to support real-time fixed point and single-precision floating point
operations using the general-purpose registers. All arithmetic instructions that execute in the core operate
on data in the GPRs. The registers have been extended to 64-bits in order to support vector instructions
defined by the SPE APU. These instructions operate on 16-bit or 32-bit data types, and produce vector or
scalar results.
3.1.3 Features
The following is a list of some of the key features of the e200z6:
• Single issue, 32-bit CPU built on the Power Architecture embedded category
• In-order execution and retirement
• Precise exception handling
• Branch target address cache
— Dedicated branch address calculation adder
— Branch target prefetching
— Branch lookahead buffers of depth 2
• Load/store unit
— Pipelined operation supports throughput of one load or store operation per cycle
• 64-bit general-purpose register file
• Memory management unit (MMU) with 32-entry fully-associative TLB and multiple page size
support
• 32 kilobyte, 8-way set associative unified cache in the MPC5554; 8 kilobyte, 2-way set-associative
unified cache in the MPC5553
• Periodic timer and watchdog functions
• Periodic system integrity may be monitored through parallel signature checks
• Signal processing extension APU supporting fixed-point and single-precision floating-point
operations, using the 64-bit general-purpose register file
• Nexus class 3 real-time development unit
• Power management
— Low power design
— Dynamic power management of execution units, caches and MMUs
3.1.3.1 Instruction Unit Features
The features of the instruction unit are the following:
• 64-bit path to cache supports fetching of two 32-bit instructions per clock
• Instruction buffer holds up to 6 sequential instructions
• Dedicated PC incrementer supporting instruction prefetches
• Branch target address cache with dedicated branch address adder, and branch lookahead logic
supporting single cycle execution of successful lookahead branches
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