Freescale Semiconductor MPC5553 - Introduction

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 3-1
Chapter 3
e200z6 Core Complex
3.1 Introduction
The core complex of the MPC5553/MPC5554 consists of the e200z6 core, a 32 Kbyte (MPC5554) or an
8 kilobyte (MPC5553) unified cache memory, a 32-entry memory management unit (MMU), a Nexus
Class 3 block, and a bus interface unit (BIU). The e200z6 core is the central processing unit (CPU) in the
MPC5553/MPC5554. The e200z6 core is part of a family of CPU cores that implement versions built on
the Power Architecture embedded category.
The host processor core of the device complies with the Power Architecture embedded category, which is
100 percent user mode compatible with the original Power PC user instruction set architecture (UISA).
However, in the Power Architecture definition, the original floating-point resources (used by a SIMD
design supporting single-precision vector and single-precision scalar operations) are provided that share
the GPRs defined for integer instructions.
Refer to the e200z6 PowerPC
TM
Core Reference Manual for more information on the e200z6 core.