Freescale Semiconductor MPC5553 - Chapter 10; Priority Management

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 10-29
The time from when the peripheral starts to drive its peripheral interrupt request to the INTC to the time
that the INTC starts to drive the interrupt request to the processor is three clocks.
10.4.1.2 Software Settable Interrupt Requests
The software set/clear interrupt registers (INTC_SSCIRx_x) support the setting or clearing of
software-settable interrupt requests. These registers contain eight independent sets of bits to set and clear
a corresponding flag bit by software. With the exception of being set by software, this flag bit behaves the
same as a flag bit set within a peripheral. This flag bit generates an interrupt request within the INTC just
like a peripheral interrupt request.
An interrupt request is triggered by software writing a 1 to the SETn bit in INTC software set/clear
interrupt registers (INTC_SSCIR0–INTC_SSCIR7). This write sets the corresponding CLRn bit, which is
a flag bit, resulting in the interrupt request. The interrupt request is cleared by writing a 1 to the CLRn bit.
Specific behavior includes the following:
• Writing a 1 to SETn leaves SETn unchanged at '0' but sets the flag bit (which is the CLRn bit).
• Writing a 0 to SETn has no effect.
• Writing a 1 to CLRn clears the flag (CLRx) bit.
• Writing a 0 to CLRn has no effect.
• If a 1 is written to a pair of SETn and CLRn bits at the same time, the flag (CLRx) is set, regardless
of whether CLRn was asserted before the write.
The time from the write to the SETn bit to the time that the INTC starts to drive the interrupt request to the
processor is four clocks.
10.4.1.3 Unique Vector for Each Interrupt Request Source
Each peripheral and software settable interrupt request is assigned a hardwired unique 9-bit vector.
Software settable interrupts 0–7 are assigned vectors 0–7, respectively. The peripheral interrupt requests
are assigned vectors 8 to as high as needed to cover all of the peripheral interrupt requests.
10.4.2 Priority Management
The asserted interrupt requests are compared to each other based on their PRIn values in INTC priority
select registers (INTC_PSR0–INTC_PSR307). The result of that comparison also is compared to PRI in
INTC current priority register (INTC_CPR). The results of those comparisons are used to manage the
priority of the ISR being executed by the processor. The LIFO also assists in managing that priority.
10.4.2.1 Current Priority and Preemption
The priority arbitrator, selector, encoder, and comparator submodules shown in Figure 10-1 are used to
compare the priority of the asserted interrupt requests to the current priority. If the priority of any asserted
peripheral or software settable interrupt request is higher than the current priority, then the interrupt request
to the processor is asserted. Also, a unique vector for the preempting peripheral or software settable
interrupt request is generated for INTC interrupt acknowledge register (INTC_IACKR), and if in hardware
vector mode, for the interrupt vector provided to the processor.