Freescale Semiconductor MPC5553 - GPIO Operation

System Interface Unit (SIU)
MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 6-107
Each IRQ pin has a programmable filter for rejecting glitches on the IRQ signals. The filter length for the
IRQ pins is specified in the external IRQ digital filter register (SIU_IDFR).
Figure 6-141. SIU DMA/Interrupt Request Diagram
6.4.4 GPIO Operation
All GPIO functionality is provided by the SIU for the MPC5553/MPC5554. Each MPC5553/MPC5554
pin that has GPIO functionality has an associated pin configuration register in the SIU where the GPIO
function is selected for the pin. In addition, each MPC5553/MPC5554 pin with GPIO functionality has an
input data register (SIU_GPDIn_n) and an output data register (SIU_GPDOn_n).
6.4.5 Internal Multiplexing
The internal multiplexing select registers SIU_ETISR, SIU_EIISR, and SIU_DISR provide selection of
the source of the input for the eQADC external trigger inputs, the SIU external interrupts, and the DSPI
signals that are used in serial and parallel chaining of the DSPI modules.
Internal multiplexing allows user selection of the input for multiplexed external signals. For each field of
each of the select registers, a multiplexor exists in the SIU. The inputs and outputs of the multiplexors are
external signals to and from the SIU.
A block diagram of the internal multiplexing feature is given in Figure 6-142. The figure shows the
multiplexing of four external signals to an output from the SIU. A two-bit SEL field from an SIU select
register is used to select the input of the multiplexor.
Interrupt
controller
DMA/
interrupt
select
•
•
•
•
•
0
1
2
3
4
15
IMUX
Interrupt
request
DMA
request
DMA
•
•
•
0
1
15
SIU_OSR
SIU_EISR
Overrun
request
EIRQ pins
or
internal
source
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt
request
SIU_DIRSR
SIU