MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 11-9
11.1.4 FMPLL Modes of Operation
The FMPLL operational mode is configured during reset. For the MPC5554, the FMPLL mode defaults
to crystal reference mode. The 324 and 416 package sizes of the MPC5553 also default to crystal reference
mode. For the MPC5554 and the 324 and 416 package sizes of the MPC5553, if the user should desire to
change from this mode, the RSTCFG
and PLLCFG[0:1] package pins must be driven to the appropriate
state for the desired mode from the time RSTOUT asserts until it negates. As shown in Table 11-1, if
RSTCFG
is not asserted during reset, the state of the PLLCFG package pins is ignored, and the FMPLL
will operate in the default crystal reference mode. The table also shows that to enter any other mode
RSTCFG must be asserted during reset.
Note that because the 208 package size of the MPC5553 has no RSTCFG pin, after reset the 208 resets to
the values of PLLCFG before reset. The device does not reset to the crystal reference mode as do the other
MPC5553/MPC5554 packages.
Table 11-1 shows clock mode selection during reset configuration for the MPC5554 and for the 416 and
324 pin packages of the MPC5553. Additional information on reset configuration options for the FMPLL
can be found in Chapter 4, “Reset.”
Table 11-1. Clock Mode Selection in 416 Pin and 324 Pin Packages
Package Pins
Clock Mode
Synthesizer Status Register
(FMPLL_SYNSR)
1
Bits
1
See Section 11.3.1.2, “Synthesizer Status Register (FMPLL_SYNSR)” for more information on these bits.
RSTCFG
PLLCFG[0] PLLCFG[1] MODE PLLSEL PLLREF
1 PLLCFG pins ignored. Crystal reference
(default mode) 1 1 1
010
001 External reference 110
000 Bypass Mode 000
0 1 1 Dual-Controller Mode 1 0 0
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