MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
20-4 Freescale Semiconductor
– RX FIFO is not empty (RFDF)
– FIFO overrun (attempt to transmit with an empty TX FIFO or serial frame received while
RX FIFO is full) (RFOF)
– FIFO under flow (slave only and SPI mode, the slave is asked to transfer data when the TX
FIFO is empty) in the MPC5553 only (TFUF)
• Modified SPI transfer formats for communication with slower peripheral devices
• Continuous serial communications clock (SCK)
• Supports all functional modes from QSPI subblock of QSMCM (MPC500 family)
When configured for DSI or CSI operation, the DSPI supports pin reduction through serialization and
deserialization.
• Serialized data sources
— eTPU_A (both MPC5553 and MPC5554), eTPU_B (for the MPC5554 only), and eMIOS
output channels
— Memory-mapped register in the DSPI
• Deserialized data destinations
— eTPU_A and eMIOS input channels
— SIU external interrupt request inputs
— Memory-mapped register in the DSPI
• Transfer initiation conditions
– Continuous
– Edge sensitive hardware trigger
– Change in data
• Support for parallel and serial chaining of DSPI modules
• Pin serialization/deserialization with interleaved SPI frames for control and diagnostics
20.1.4 Modes of Operation
The DSPI has four modes of operation. These modes can be divided into two categories; module-specific
modes such as master, slave, and module disable modes, and an MCU-specific mode (debug mode). a
second category that is an MCU-specific mode: debug mode
The module-specific modes are entered by host software writing to a register. The MCU-specific mode is
controlled by signals external to the DSPI. The MCU-specific mode is a mode that the entire
MPC5553/MPC5554 may enter, in parallel to the DSPI being in one of its module-specific modes.
20.1.4.1 Master Mode
Master mode allows the DSPI to initiate and control serial communication. In this mode the SCK, PCSn
and SOUT signals are controlled by the DSPI and configured as outputs. For more information, see
Section 20.4.1.1, “Master Mode.”
20.1.4.2 Slave Mode
Slave mode allows the DSPI to communicate with SPI/DSI bus masters. In this mode the DSPI responds
to externally controlled serial transfers. The DSPI cannot initiate serial transfers in slave mode. In slave
mode, the SCK signal and the PCS0/SS signal are configured as inputs and provided by a bus master.
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