MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 22-5
22.2.2 Detailed Signal Description
22.2.2.1 CNRXx
This pin is the receive pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
22.2.2.2 CNTXx
This pin is the transmit pin to the CAN bus transceiver. The dominant state is represented by logic level 0.
The recessive state is represented by logic level 1.
22.3 Memory Map/Register Definition
This section describes the registers and data structures in the FlexCAN2 module. The addresses presented
here are relative to the base address of the module.
The address space occupied by FlexCAN2 is continuous: 128 bytes for registers starting at the module base
address, extra space for MB storage, and 1024 bytes for 64 MBs.
22.3.1 Memory Map
The complete memory map for a FlexCAN2 module with its 64 MBs is shown in Table 22-2. Except for
the base addresses, the three (MPC5554) or two (MPC5553) FlexCAN2 modules have identical memory
maps. Each individual register is identified by its complete name and the corresponding mnemonic.
Table 22-2. Module Memory Map
Address Register Name Register Description Size (bits)
Base = 0xFFFC_0000 (FlexCAN A)
1
Base = 0xFFFC_4000 (FlexCAN B)
1
Base = 0xFFFC_8000 (FlexCAN C)
1
CANx_MCR Module configuration register 32
Base + 0x0004 CANx_CR Control register 32
Base + 0x0008 CANx_TIMER Free running timer 32
Base + 0x000C
— Reserved —
Base + 0x0010 CANx_RXGMASK RX global mask 32
Base + 0x0014 CANx_RX14MASK RX buffer 14 mask 32
Base + 0x0018 CANx_RX15MASK RX buffer 15 mask 32
Base + 0x001C CANx_ECR Error counter register 32
Base + 0x0020 CANx_ESR Error and status register 32
Base + 0x0024 CANx_IMRH Interrupt masks high register 32
Base + 0x0028 CANx_IMRL Interrupt masks low register 32
Base + 0x002C CANx_IFRH Interrupt flags high register 32
Base + 0x0030 CANx_IFRL Interrupt flags low register 32
Base + 0x0034–
Base + 0x005F
— Reserved —
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