MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 22-31
The bus interface unit continues to operate, enabling the CPU to access memory mapped registers except
the free running timer, the CANx_ECR and the message buffers, which cannot be accessed when the
module is disabled. Exiting from this mode is done by negating the CANx_MCR[MDIS] bit, which will
resume the clocks and negate the CANx_MCR[MDISACK] bit.
22.4.7 Interrupts
The module can generate interrupts from 20 interrupt sources (16 interrupts due to message buffers, two
interrupts due to bus off and error conditions and two interrupts for the OR'd MB16–MB31 and
MB32–63).
Each of the 64 message buffers can be an interrupt source, if its corresponding CANx_IMRH or
CANx_IMRL bit is set. There is no distinction between TX and RX interrupts for a particular buffer, under
the assumption that the buffer is initialized for either transmission or reception. Each of the buffers has
assigned a flag bit in the CANx_IFRH or CANx_IFRL registers. The bit is set when the corresponding
buffer completes a successful transmission/reception and is cleared when the CPU writes it to 1.
A combined interrupt for each of two MB groups, MB16–MB31 and MB32–MB63, is also generated by
an OR of all the interrupt sources from the associated MBs. This interrupt gets generated when any of the
MBs generates an interrupt. In this case the CPU must read the CANx_IFRH and CANx_IFRL registers
to determine which MB caused the interrupt.
The other two interrupt sources (bus off and error) generate interrupts like the MB interrupt sources, and
can be read from CANx_ESR. The bus off and error interrupt mask bits are located in the CANx_CR.
22.4.8 Bus Interface
The CPU access to FlexCAN2 registers are subject to the following rules:
• Read and write access to unimplemented or reserved address space also results in access error. Any
access to unimplemented MB locations results in access error.
• For a FlexCAN2 configuration that uses less than the total number of MBs and MAXMB is set
accordingly, the remaining MB space can be used as general-purpose RAM space. Byte, word and
long word accesses are allowed to the unused MB space.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
22.5 Initialization/Application Information
This section provides instructions for initializing the FlexCAN2 module.
22.5.1 FlexCAN2 Initialization Sequence
The FlexCAN2 module can be reset in three ways:
• MCU-level hard reset, which resets all memory mapped registers asynchronously
• MCU-level soft reset, which resets some of the memory mapped registers synchronously (refer to
Table 22-2 to see what registers are affected by soft reset)
• SOFTRST bit in CANx_MCR, which has the same effect as the MCU level soft reset
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