Freescale Semiconductor MPC5553 - Page 790

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 19-35
19.3.2.14 eQADC CFIFO Registers (EQADC_CF[0–5]Rn)
EQADC_CF[0–5]Rn provide visibility of the contents of a CFIFO for debugging purposes. Each CFIFO
has four registers that are uniquely mapped to its four 32-bit entries. Refer to Section 19.4.3, “eQADC
Command FIFOs,” for more information on CFIFOs. These registers are read only. Data written to these
registers is ignored.
19.3.2.15 eQADC RFIFO Registers (EQADC_RF[0–5]Rn)
EQADC_RF[0–5]Rn provide visibility of the contents of a RFIFO for debugging purposes. Each RFIFO
has four registers which are uniquely mapped to its four 16-bit entries. Refer to Section 19.4.4, “Result
FIFOs,” for more information on RFIFOs. These registers are read only. Data written to these registers is
ignored.
0123456789101112131415
R CFIFO[0–5]_DATAn
W
Reset0000000000000000
Reg Addr CFIFO0: Base + 0x0100 (CF0R0); Base + 0x0104 (CF0R1); Base + 0x0108 (CF0R2); Base + 0x010C (CF0R3)
CFIFO1:Base + 0x0140 (CF1R0); Base + 0x0144 (CF1R1); Base + 0x0148 (CF1R2);Base + 0x014C (CF1R3)
CFIFO2: Base + 0x0180 (CF2R0); Base + 0x0184 (CF2R1); Base + 0x0188 (CF2R2); Base + 0x018C (CF2R3)
CFIFO3: Base + 0x01C0 (CF3R0); Base + 0x01C4 (CF3R1); Base + 0x01C8 (CF3R2); Base + 0x01CC (CF3R3)
CFIFO4: Base + 0x0200 (CF4R0); Base + 0x0204 (CF4R1); Base + 0x0208 (CF4R2); Base + 0x020C (CF4R3)
CFIFO5: Base + 0x0240 (CF5R0); Base + 0x0244 (CF5R1); Base + 0x0248 (CF5R2); Base + 0x024C (CF5R3)
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CFIFO[0–5]_DATAn
W
Reset0000000000000000
Reg Addr CFIFO0: Base + 0x0100 (CF0R0); Base + 0x0104 (CF0R1); Base + 0x0108 (CF0R2); Base + 0x010C (CF0R3)
CFIFO1:Base + 0x0140 (CF1R0); Base + 0x0144 (CF1R1); Base + 0x0148 (CF1R2);Base + 0x014C (CF1R3)
CFIFO2: Base + 0x0180 (CF2R0); Base + 0x0184 (CF2R1); Base + 0x0188 (CF2R2); Base + 0x018C (CF2R3)
CFIFO3: Base + 0x01C0 (CF3R0); Base + 0x01C4 (CF3R1); Base + 0x01C8 (CF3R2); Base + 0x01CC (CF3R3)
CFIFO4: Base + 0x0200 (CF4R0); Base + 0x0204 (CF4R1); Base + 0x0208 (CF4R2); Base + 0x020C (CF4R3)
CFIFO5: Base + 0x0240 (CF5R0); Base + 0x0244 (CF5R1); Base + 0x0248 (CF5R2); Base + 0x024C (CF5R3)
Figure 19-17. eQADC CFIF0[0–5] Registers (EQADC_CF[0–5]Rn)
Table 19-23. EQADC_CF[0–5]Rn Field Descriptions
Bits Name Description
0–31 CFIFO[0–5]_DATAn
[0:31]
CFIFO[0–5]_datan. Returns the value stored within the entry of CFIFO[0–5]. Each
CFIFO is composed of four 32-bit entries, with register 0 being mapped to the entry
with the smallest memory mapped address.