MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
9-16 Freescale Semiconductor
9.3.1.7 eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_EEIRH or EDMA_EEIRL to enable the error interrupt for a given channel. The data value on a
register write causes the corresponding bit in the EDMA_EEIRH or EDMA_EEIRL to be set. Setting bit
1 (SEEIn) provides a global set function, forcing the entire contents of EDMA_EEIRH or EDMA_EEIRL
to be asserted. Reads of this register return all zeroes. For the MPC5553, bit 2 (SEEI1) is not used.
01234567
R00000000
W CERQ[0:6]
Reset00000000
Reg Addr Base + 0x0019
Figure 9-9. eDMA Clear Enable Request Register (EDMA_CERQR)
Table 9-7. EDMA_CERQR Field Descriptions
Bits Name Description
0 — Reserved.
1–7 CERQ
[0:6]
Clear enable request.
0–63 Clear corresponding bit in EDMA_ERQRH or EDMA_ERQRL
64–127 Clear all bits in EDMA_ERQRH and EDMA_ERQRL
Note: For the MPC5553, the value 32-63 [bit 2 (CERQ1)] is reserved.
01234567
R00000000
W SEEI[0:6]
Reset00000000
Reg Addr Base + 0x001A
Figure 9-10. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 9-8. EDMA_SEEIR Field Descriptions
Bits Name Description
0 — Reserved.
1–7 SEEI
[0:6]
Set enable error interrupt.
0–63 Set the corresponding bit in EDMA_EEIRH or EDMA_EEIRL
64–127 Set all bits in EDMA_EEIRH and EDMA_EEIRL
Note: For the MPC5553, the value 32-63 [bit 2 (SEEI1)] is reserved.
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