MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 1-7
— Current controlled oscillator (ICO) range from 50 MHz to maximum device frequency
— Reduced frequency divider (RFD) for reduced frequency operation without re-lock
— Four selectable modes of operation
— Programmable frequency modulation
— Lock detect circuitry continuously monitors lock status
— Loss of clock (LOC) detection for reference and feedback clocks
— Self-clocked mode (SCM) operation
— On-chip loop filter (reduces number of external components required)
— Engineering clock output
• External bus interface (EBI)
— 1.8V–3.3V nominal I/O voltage
— Memory controller with support for various memory types
— MPC5554 specifications:
– 32-bit data bus, 24-bit address bus with transfer size indication
— MPC5553 specifications:
– 416 BGA: 32-bit data bus, 24-bit address bus without transfer size indication
– 324 BGA: 16-bit data bus, 20-bit address bus (configurable to 24-bit address bus)
– 208 MAPBGA: no external bus
— Selectable drive strengths through pad control in SIU
— Configurable bus speed modes
— Support for external master accesses to internal addresses
— Burst support
— Bus monitor
– User selectable
– Programmable timeout period (with 8 external bus clock resolution)
— Chip selects
– In both the MPC5553 and MPC5554, four chip select (CS
[0:3]) signals; but the MPC5553
has no CS
signals in the 208 MAPBGA package.
– In the MPC5553 only, support for dynamic calibration with up to three calibration chip
selects (CAL_CS
[0] and CAL_CS[2:3])
— Configurable wait states
• System integration unit (SIU)
— Centralized GPIO control of 214 (MPC5554) or 198 (MPC5553) I/O and bus pins
— Centralized pad control on a per-pin basis
— System reset monitoring and generation
— External interrupt inputs, filtering and control
— Internal multiplexer submodule (SIU_DISR, SIU_ETISR, SIU_EIISR)
• Error correction status module (ECSM)
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