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MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
1-8 Freescale Semiconductor
Configurable error-correcting codes (ECC) reporting for internal SRAM and flash memories
On-chip flash
2 Mbytes (MPC5554) or 1.5 Mbytes (MPC5553) burst flash memory
256K 64-bit (MPC5554) or 196K 64-bit (MPC5553) configuration
Censorship protection scheme to prevent flash content visibility
Hardware read-while-write feature that allows blocks to be erased/programmed while other
blocks are being read (used for EEPROM emulation and data calibration)
20 blocks (MPC5554) or 16 blocks (MPC5553) with sizes ranging from 16 Kbytes to
128 Kbytes to support features such as boot block, operating system block, and EEPROM
emulation
Read while write with multiple partitions
Page programming mode to support rapid end of line programming
Hardware programming state machine
Configurable cache memory, 32 kilobyte (MPC5554) / 8 kilobyte (MPC5553)
8-way set-associative, unified (instruction and data) cache in the MPC5554
2-way set-associative unified (instruction and data) cache in the MPC5553
On-chip internal static RAM (SRAM)
64 kilobyte general-purpose RAM of which 32 kilobytes can be configured for standby
operation
ECC performs single bit correction, double bit error detection
Boot assist module (BAM)
Enables and manages the transition of MCU from reset to user code execution in the following
configurations:
User application can boot from internal or external flash memory
Download and execution of code via FlexCAN or eSCI
Enhanced modular I/O system (eMIOS)
24 orthogonal channels with double action, PWM, and modulus counter functionality
Supports all DASM and PWM modes of MIOS14 (MPC5xx)
Four selectable time bases plus shared time or angle counter bus
DMA and interrupt request support
Motor control capability
Enhanced time processor unit (eTPU)
MPC5554 has two eTPU engines, MPC5553 has one engine
Each eTPU engine is an event-triggered timer subsystem
High level assembler/compiler
32 channels per engine
24-bit timer resolution

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