MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-73
• No memory controller support for external masters
— Must configure each master in multi-master system to drive its own chip selects
• Changes in bit fields:
— Removed these variable timing attributes from option register: CSNT, ACS, TRLX, EHTR
— Removed LBDIP base register bit, now late BDIP assertion is default behavior
— Modified TSIZ[0:1] functionality to only indicate size of current transfer, not give information
on ensuing transfers that may be part of the same atomic sequence
— The BL field of the base register has inverted logic from the MPC56x devices (0 = 8-beat burst
on the MPC5500, 1 = 8-beat burst on the MPC56x)
• Removed reservation support on external bus
• Removed address type (AT), write-protect (WP), and dual-mapping features because these
functions can be replicated by memory management unit (MMU) in e200z6 core
• Removed support for 8-bit ports
• Removed boot chip select operation
— On-chip boot assist module (BAM) handles boot (and configuration of EBI registers)
• Open drain mode and pull-up resistors no longer required for multi-master systems, extra cycle
needed to switch between masters
• Modified arbitration protocol to require extra cycles when switching between masters
• Added support for 32-bit coherent read and write non-chip select accesses in 16-bit data bus mode
• Misaligned accesses are not supported
• The MPC5553 has calibration features implemented by four calibration chip selects
• Removed support for 3-master systems
• Address decoding for external master accesses uses 4-bit code to determine internal slave instead
of straight address decode
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