MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-35
Figure 12-21. Read After Write to the Same CS Bank
12.4.2.5 Burst Transfer
The EBI supports wrapping 32-byte critical-doubleword-first burst transfers. Bursting is supported only
for internally-requested cache-line size (32-byte) read accesses to external devices that use the chip
selects
1
. Accesses from an external master or to devices operating without a chip select are always single
beat. If an internal request to the EBI indicates a size of less than 32 bytes, the request is fulfilled by
running one or more single-beat external transfers, not by an external burst transfer.
An 8-word wrapping burst reads eight 32-bit words by supplying a starting address that points to one of
the words (doubleword aligned) and requiring the memory device to sequentially drive each word on the
data bus. The selected slave device must internally increment ADDR[27:29] (also ADDR30 in the case of
1. Except for the special case of a 32-bit non-chip select access in 16-bit data bus mode. See Section 12.4.2.11.
ADDR[8:31]
TS
DATA[0:31]
TA
RD_WR
DATA is valid
TSIZ[0:1]
BDIP
WE
CSx
’00’
DATA is valid
CLKOUT
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