MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
Freescale Semiconductor 12-69
of wait states to work with the access time of the asynchronous memory, just as done for a synchronous
memory.
12.5.3.1 Example Wait State Calculation
This example applies to any chip select memory, synchronous or asynchronous.
As an example, say we have a memory with 50ns access time, and we are running the external bus
@66MHz (CLKOUT period: 15.2ns). Assume the input data spec for the MCU is 4ns.
number of wait states = (access time) / (CLKOUT period) + (0 or 1) (depending on setup time)
50/15.2 = 3 with 4.4ns remaining (so we need at least three wait states, now check setup time)
15.2-4.4=10.8ns (this is the achieved input data setup time)
Because actual input setup (10.8ns) is greater than the input setup spec (4.0ns), three wait states is
sufficient. If the actual input setup was less than 4.0ns, we would have to use four wait states instead.
12.5.3.2 Timing and Connections for Asynchronous Memories
The connections to an asynchronous memory are the same as for a synchronous memory, except that the
CLKOUT, TS, and BDIP signals are not used. Figure 12-52 shows a block diagram of an MCU connected
to an asynchronous memory.
Figure 12-52. MCU Connected to Asynchronous Memory
Figure 12-53 shows a timing diagram of a read operation to a 16-bit asynchronous memory using three
wait states. Figure 12-54 shows a timing diagram of a write operation to a 16-bit asynchronous memory
using three wait states.
Flash memories typically use one WE signal as shown, RAMs use 2 or 4 (16-bit or 32-bit).*
WE
0/BE0
ADDR[9:30]
DATA[0:15]
OE
MCU
WE
*
A[0:21]
D[0:15]
OE
Asynchronous
Memory
CS0
CE
CAL_CS0
Note: On a 32-bit bus, RAM memories use all four WE/BE[0:3]. On a 16-bit bus, one
RAM memory uses WE/BE[0:1] and the other uses WE/BE[2:3].
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