MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
1-10 Freescale Semiconductor
— Advanced error detection, and optional parity generation and detection
— Word length programmable as 8 or 9 bits
— Separately enabled transmitter and receiver
— LIN Support
— DMA support
— Interrupt request support
• Three (MPC5554) or two (MPC5553) FlexCANs
— 64 message buffers each
— Full implementation of the CAN protocol specification, Version 2.0B
— Based on and including all existing features of the Freescale TouCAN module
— Programmable acceptance filters
— Short latency time for high priority transmit messages
— Arbitration scheme according to message ID or message buffer number
— Listen only mode capabilities
— Programmable clock source: system clock or oscillator clock
• Nexus development interface (NDI)
— Per IEEE-ISTO 5001-2003
— Real time development support for Power Architecture core and eTPU engines through Nexus
class 3 (some Class 4 support)
— Data trace of eDMA accesses
— Read and write access
— Configured via the IEEE 1149.1 (JTAG) port
— High bandwidth mode for fast message transmission
— Reduced bandwidth mode for reduced pin usage
•IEEE 1149.1 JTAG controller (JTAGC)
—IEEE 1149.1-2001 test access port (TAP) interface
— A JCOMP input that provides the ability to share the TAP. Selectable modes of operation
include JTAGC/debug or normal system operation.
— A 5-bit instruction register that supports IEEE 1149.1-2001 defined instructions.
— A 5-bit instruction register that supports additional public instructions.
— Three test data registers: a bypass register, a boundary scan register, and a device identification
register.
— A TAP controller state machine that controls the operation of the data registers, instruction
register and associated circuitry.
• Voltage regulator controller
— Provides a low cost solution to power the core logic. It reduces the number of power supplies
required from the customer power supply chip.
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