MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
8-10 Freescale Semiconductor
8.2.1.10 Flash ECC Data Low Registers (ECSM_FEDRL)
The ECSM_FEDRH and ECSM_FEDRL are 32-bit registers for capturing the data associated with the
last, properly-enabled ECC event in the flash memory. Depending on the state of the ECSM_ECR, an ECC
event in the flash causes the address, attributes and data associated with the access to be loaded into the
ECSM_FEAR, ECSM_FEMR, ECSM_FEAT and ECSM_FEDRs, and the appropriate flag (FNCE) in the
ECSM_ESR to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
0123456789101112131415
RFEDH
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x58
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RFEDH
W
ResetUUUUUUUUUUUUUUUU
Reg Addr Base + 0x0058
1
“U” signifies a bit that is uninitialized.
Figure 8-7. Flash ECC Data High Register (ECSM_FEDRH)
Table 8-9. ECSM_FEDRH Field Descriptions
Bits Name Description
0–31 FEDH
[0:31]
Flash ECC data. Contains the data associated with the faulting access of the last,
properly-enabled flash ECC event. The register contains the data value taken directly from
the data bus. The reset value of this field is undefined.
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