Freescale Semiconductor MPC5553 - Page 161

MPC5553/MPC5554 Microcontroller Reference Manual, Rev. 5
4-18 Freescale Semiconductor
Figure 4-6. Internal Reset Flow Diagram
False
True
False False
Assert
RSTOUT
Wait 2400
1
Clock Cycles
True True
Software
System Reset
Asserted
?
Internal
Reset
Asserted
?
Software
External Reset
Asserted
?
Assert Internal
Resets &
RSTOUT
A
Apply
WKPCFG Pin
True
False
RSTCFG
Asserted
?
Loss
of Lock
Negated
Default PLL
Configuration
Applied,
Not Latched
False
True
Wait 2400
1
Clock Cycles
Latch
WKPCFG Pin
RSTCFG
Asserted
?
Latch BOOTCFG
Values
Wait 4
Clock Cycles
Update Reset
Status Register
Negate Internal
Resets &
RSTOUT
Latch Default
Boot Configuration
False
True
Entry Point from
External Reset
Flow & POR
The clock count is dependent on the configuration of the FMPLL (refer to Section 5.3.1.2, ‘RSTOUT
’).
If the FMPLL is configured in 1:1 (dual controller) or bypass mode, this clock count is 16000.
1
False
True
Wait 4
Clock Cycles
Latch PLLCFG
Values
Latch Default
PLL Configuration
?
PLLCFG Pins
Applied,
Not Latched
NOTES:
Reset
Request
Negated
?